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HCF40108B
4 x 4 MULTIPORT REGISTER
s s
s s s
s
s
s s s
s s
ONE INPUT AND TWO OUTPUT BUSES UNLIMITED EXPANSION IN BIT AND WORD DIRECTION DATA LINES HAVE LATCHED INPUTS 3-STATE OUTPUTS SEPARATE CONTROL OF EACH BUS, ALLOWING SIMULTANEOUS INDEPENDENT READING AND ANY OF FOUR REGISTERS ON BUS A AND BUS B AND INDEPENDENT WRITING INTO ANY OF THE FOUR REGISTERS 40108B IS PIN-COMPATIBLE WITH INDUSTRY TYPE MC14580 STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
SOP
ORDER CODES
PACKAGE SOP TUBE HCF40108BM1 T&R HCF40108M013TR
DESCRIPTION HCF40108B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in SOP packages. HCF40108B is a 4 x 4 multiport register containing PIN CONNECTION
four 4-bit registers, a write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high impedance state. The high impedance third state provides the outputs with the capability of being connected to the bus lines in a bus organized system without the need for interface or pull-up components. When the WRITE ENABLE input is high, all data input lines are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines. When WRITE ENABLE is low, the CLOCK is inhibited and no new data is entered. In either case, the contents of any word may be accessed via the read address lines independent of the state of the CLOCK input.
September 2002
1/11
HCF40108B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 4, 5, 6, 7 22, 23, 2, 1 20, 19, 18, 17 16 15 21 3 8, 9 10, 11 13, 14 12 24 SYMBOL NAME AND FUNCTION
Q0A to Q3A Word A Output Q0B to Q3B Word B Output D0 to D3 CLOCK WRITE ENABLE 3-STATE B 3-STATE A WRITE 0, WRITE 1 READ 0B, READ 1B READ 0A, READ 1A VSS VDD Data Inputs Clock Input Write Enable Input 3 State Output 3 State Output Write Address Inputs Read Address Inputs Read Address Inputs Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
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HCF40108B
LOGIC DIAGRAM
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HCF40108B
SCHEMATIC DIAGRAM
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HCF40108B
TRUTH TABLE
CLOCK Write Write 1 Write 2 Enable H H X X H L X X X S1 S1 X L L X X S2 S2 X L L X X Read 1A S1 S1 X L L H X Read 0A S2 S2 X H H L X Read 1B S1 S1 X H H L X Read 0B S2 S2 X L L H X Enable Enable A B H H L H H H H H L L H H X H Dn H L DnA H L QnB H L
Z Z Z Dn to Word 1 Word 2 word 0 Out Out Word 0 Word 1 Word 2 not Out Out altered Word 2 Word 1 X Out Out X NC NC
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
5/11
HCF40108B
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 10-4 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current 3-State Output Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input Any Input
0.1 0.4
7.5
1 12
1 12
A A
pF
IOZ CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
6/11
HCF40108B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 360 140 100 300 120 85 100 50 40 130 60 50 100 50 40 -95 -35 -20 125 50 35 125 50 35 Max. 720 280 200 600 240 170 200 100 80 260 120 100 200 100 80 ns Unit
tPHL tPLH Propagation Delay Time Clock or Write Enable to Q Propagation Delay Time Read or Write Address to Q tPZH tPHZ 3-State Disable Delay Time tPZL tPLZ 3-State Display Delay Time
ns
ns
ns
tTHL tTLH Output Transition Time
ns
tsetup
Setup Time Data to Clock ts(D) Setup Time Write Enable to Clock ts(WE) Setup Time Write Address to Clock ts(WA)
0 0 0 250 100 70 250 100 70
ns
ns
ns 15 5 5
tr, ts
Clock Rise and Fall Time
ns
thold
Hold Time Data to Clock ts(D) Hold Time Write Enable to Clock ts(WE) Hold Time Write Address to Clock ts(WA)
tW
Clock Pulse Width Clock or Write Enable tW(CL)
tW
Clock Pulse Width Write Address tW(WA)
fCL
Maximum Clock Input Frequency
220 100 80 270 130 80 330 140 90 350 130 90 300 150 90 1.5 3.5 4.5
110 50 40 135 65 40 165 70 45 175 65 45 150 75 45 3 7 9
ns
ns
ns
ns
ns
MHz
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HCF40108B
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
SWITCH Open VDD VSS
WAVEFORM : ENABLE AND DISABLE TIME
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HCF40108B
SWITCHING WAVEFORM
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HCF40108B
SO-24 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 8 (max.) 0.291 0.020 15.60 10.65 0.35 0.23 0.5 45 (typ.) 0.598 0.393 0.050 0.550 0.300 0.050 0.614 0.419 0.1 TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. TYP. MAX. 0.104 0.008 0.096 0.019 0.012 inch
L
a2
e3 D
E
24
13
1
1
2
F
a1
s
10/11
b1
PO13T
b
e
A
C
c1
HCF40108B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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